Peripheral component interconnect express interface device and system including the same

ABSTRACT

Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean patent application number 10-2021-0022109 filed on Feb. 18, 2021,the entire disclosure of which is incorporated by reference herein.

BACKGROUND Field of Invention

Various embodiments of the present disclosure generally relate to anelectronic device, and more particularly to a peripheral componentinterconnect express (PCIe) interface device and a system including thePCIe interface device.

Description of Related Art

Peripheral Component Interconnect Express (PCIe) is an interface havinga serial structure for data communication. A PCIe-based storage devicesupports a multi-port and a multi-function. The PCIe-based storagedevice may be virtualized or non-virtualized, and may achieve Quality ofService (QoS) of a host input and output (I/O) command through one ormore PCIe functions.

A storage device is a device configured to store data under the controlof a host device, such as a computer, a smartphone, or the like. Thestorage device may include a memory device in which data is stored and amemory controller configured to control the memory device. The memorydevice is generally classified into a volatile memory device and anonvolatile memory device.

The volatile memory device is a memory device configured to store dataonly when power is supplied thereto and to cause the stored data to beerased when a power supply is interrupted. The volatile memory deviceincludes a Static Random Access Memory (SRAM), a Dynamic Random AccessMemory (DRAM), and the like.

The nonvolatile memory device is a memory device configured such thatdata is not erased even though a power supply is interrupted, andincludes a Read Only Memory (ROM), a Programmable ROM (PROM), anElectrically Programmable ROM (EPROM), an Electrically Erasable andProgrammable ROM (EEPROM), a flash memory, and the like.

SUMMARY

Various embodiments of the present disclosure are directed to a PCIeinterface device capable of detecting the trigger points of occurringevents using a no operation (NOP) data link layer packet (DLLP) and asystem including the PCIe interface device.

An embodiment of the present disclosure may provide for a PCIe interfacedevice. The PCIe interface device may include a NOP DLLP generatorconfigured to generate a No Operation (NOP) data link layer packet(DLLP) including event information representing an event in response tothe occurrence of the event, and a transmitter configured to transmitthe NOP DLLP to an external device through a link including a pluralityof lanes.

An embodiment of the present disclosure may provide for a PCIe system.The PCIe system may include a first PCIe device configured to generate aNo Operation (NOP) data link layer packet (DLLP) including eventinformation representing an event in response to the occurrence of theevent and to transmit the NOP DLLP through a link including a pluralityof lanes, and a second PCIe device configured to, when the NOP DLLP isreceived from the first PCIe device, perform a dump operation forstoring information about data and packets transmitted and receivedduring a set time period including the time at which the NOP DLLP isreceived.

An embodiment of the present disclosure may provide for a PCIe system.The PCIe system may include a first PCIe device configured to generate aNo Operation (NOP) data link layer packet (DLLP) including eventinformation representing an event in response to the occurrence of theevent and to transmit the NOP DLLP through a link including a pluralityof lanes, a second PCIe device coupled to the first PCIe device throughthe link and configured to transmit and receive a packet including theNOP DLLP to and from the first PCIe device, and a protocol analyzercoupled to the link and configured to monitor the packet transmitted andreceived between the first PCIe device and the second PCIe devicethrough the link and to perform a dump operation for storing informationabout a communication environment based on the event information whendetecting the NOP DLLP.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a PCIe computing system according to anembodiment of the present disclosure.

FIG. 2 is a diagram illustrating a connection between PCIe devicesaccording to an embodiment of the present disclosure.

FIG. 3 is a diagram illustrating a lane according to an embodiment ofthe present disclosure.

FIG. 4 is a diagram illustrating a PCIe interface according to anembodiment of the present disclosure.

FIG. 5 is a diagram illustrating the configuration of a packet accordingto an embodiment of the present disclosure.

FIG. 6 is a diagram illustrating a DLLP according to an embodiment ofthe present disclosure.

FIG. 7 is a diagram illustrating the structure of a NOP DLLP accordingto an embodiment of the present disclosure.

FIG. 8 is a diagram illustrating event information according to anembodiment of the present disclosure.

FIG. 9 is a diagram illustrating event information according to anembodiment of the present disclosure.

FIG. 10 is a diagram illustrating a link state of a PCIe deviceaccording to an embodiment of the present disclosure.

FIG. 11 is a diagram illustrating a protocol analyzer according to anembodiment of the present disclosure.

FIG. 12 is a diagram illustrating a first PCIe interface according to anembodiment of the present disclosure.

DETAILED DESCRIPTION

Specific structural or functional descriptions of the embodiments of thepresent disclosure introduced in this specification or application areonly for description of the embodiments of the present disclosure. Thedescriptions should not be construed as being limited to the embodimentsdescribed in the specification or application.

The present disclosure will now be described in detail based onembodiments. The present disclosure may, however, be embodied in manydifferent forms and should not be construed as being limited to only theembodiments set forth herein, but should be construed as coveringmodifications, equivalents or alternatives falling within ideas andtechnical scopes of the present disclosure. However, this is notintended to limit the present disclosure to particular modes ofpractice, and it is to be appreciated that all changes, equivalents, andsubstitutes that do not depart from the spirit and technical scope ofthe present disclosure are encompassed in the present disclosure.Detailed description of functions and structures well known to thoseskilled in the art will be omitted to avoid obscuring the subject matterof the present disclosure. This aims to omit unnecessary description tomake the gist of the present disclosure clear.

Hereinafter, various embodiments of the present disclosure will bedescribed in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a PCIe computing system 10000 accordingto an embodiment of the present disclosure.

Referring to FIG. 1, the PCIe computing system 10000 may include acentral processing unit (CPU) 1010, a root complex 1020, a memory 1030,a switch 1040, a Peripheral Component Interconnect (PCI) Express (PCIe)endpoint 1050, a legacy endpoint 1060, and a PCIe bridge 1070.

The PCIe computing system 10000 may be an electronic device supportingcommunication using a PCIe interface. The PCIe computing system 10000may be a PC, a laptop computer, or a mobile computing device, and mayinclude an expansion card, an expansion board, an adapter card, anadd-in card, or an accessory card. Also, the PCIe computing system 10000may include a printed circuit board (PCB) that is insertable into anelectrical connector or an expansion slot on the motherboard of the PCIecomputing system 10000 in order to provide additional functions to thePCIe computing system 10000 through an expansion bus. Also, the PCIecomputing system 10000 may include a storage device such as solid statedrives (SSD), and may include a graphics card, a network card, a USBcard, or the like.

The central processing unit 1010 is electrically coupled to therespective components of the PCIe computing system 10000, and maycontrol each operation of the PCIe computing system 10000. Specifically,the central processing unit 1010 may control the components of hardwareor software coupled to the central processing unit 1010 by running anoperating system or applications, and may process various types of dataand perform operations. Also, the central processing unit 1010 mayexecute software or an application for controlling the operation of thePCIe computing system 10000.

The root complex 1020 may be a root hub, a controller hub, or a rootcontroller in the interconnect architecture of Peripheral ComponentInterconnect (PCI) Express (PCIe). For example, the root complex 1020may include a chipset, a memory controller hub (MCH), a northbridge, aninterconnect controller hub (ICH), a southbridge, and a rootcontroller/hub. Also, the root complex 1020 may couple the centralprocessing unit 1010 and the memory 1030 to an I/O hierarchy. The rootcomplex 1020 may support Peer-to-Peer (P2P) routing. The root complex1020 may include at least one host bridge and a root port. The rootcomplex 1020 may support one or more Peripheral Component InterconnectExpress (PCIe) ports.

The memory 1030 may store data, commands, or program code required forthe operation of the PCIe computing system 10000. In an embodiment, thememory 1030 may store program code that is capable of operating toexecute one or more operating systems (OS) and virtual machines (VM) andprogram code executing Virtualization Intermediary (VI) for managing thevirtual machines. Also, the memory 1030 may be implemented as a volatilememory device such as a DRAM, an SRAM or the like.

The switch 1040 may route a packet or a message upstream or downstream.Specifically, the switch 1040 may route a packet or a message upstreamfrom the PCIe endpoint 1050 to the root complex 1020, or may route apacket or a message downstream from the root complex 1020 to the PCIeendpoint 1050.

The switch 1040 may be referred to as the logic assembly of a pluralityof virtual PCI-to-PCI bridge devices. The devices that can be coupled tothe switch 1040 may include any internal or external devices orcomponents coupled to an electronic system, such as an I/O device, aNetwork Interface Controller (NIC), an add-in card, an audio processor,a network processor, a hard drive, a storage device, a CD/DVD ROM, amonitor, a printer, a mouse, a keyboard, a router, a portable storagedevice, a firewire device, a Universal Serial Bus (USB) device, ascanner, and other input/output devices.

The PCIe endpoint 1050 and the legacy endpoint 1060 may serve as therequestor or completer of a PCIe transaction. A transaction layer packet(TLP) transmitted and received by the PCIe endpoint 1050 and the legacyendpoint 1060 must provide a configuration space header. Also, the PCIeendpoint 1050 and the legacy endpoint 1060 must provide a configurationrequest as a completer.

The PCIe endpoint 1050 and the legacy endpoint 1060 may be identifieddepending on the size of a memory transaction. For example, when amemory transaction exceeding 4GB is possible, the endpoint may be thePCIe endpoint 1050, and when a memory transaction exceeding 4GB isimpossible, the endpoint may be the legacy endpoint 1060. The PCIeendpoint 1050 is not allowed to generate an I/O request, but the legacyendpoint 1060 may provide or generate an I/O request. Also, the PCIeendpoint 1050 may transmit and receive a TLP to and from the rootcomplex 1020. Also, PCI/PCI-X may transmit and receive a TLP to and fromthe root complex 1020 via the PCIe bridge 1070. The PCIe endpoint 1050or the legacy endpoint 1060 may transmit and receive a TLP to and fromthe switch 1040.

FIG. 2 is a diagram illustrating a connection between a first PCIedevice 1000 and a second PCIe device 2000 according to an embodiment ofthe present disclosure.

Referring to FIG. 2, the PCIe devices 1000 and 2000 may include a PCIeinterface 100 and 200, respectively. Each PCIe device may be anelectronic device that supports a PCIe protocol using the correspondingPCIe interface. For example, the first PCIe device 1000 or the secondPCIe device 2000 may be any of the root complex 1020, the switch 1040,the PCIe endpoint 1050, the legacy endpoint 1060, and the PCIe bridge1070 of FIG. 1.

The first PCIe device 1000 may communicate with the second PCIe device2000 using a first PCIe interface 100. The second PCIe device 2000 maycommunicate with the first PCIe device 1000 using a second PCIeinterface 200. Specifically, the first PCIe device 1000 may convert thedata to transmit to the second PCIe device 2000 into a protocol suitablefor communication using the first PCIe interface 100. The second PCIedevice 2000 may convert the data to transmit to the first PCIe device1000 into a protocol suitable for communication using the second PCIeinterface 200. For example, the first PCIe device 1000 may convert thedata to transmit to the second PCIe device 2000 into a PCIe protocolusing the first PCIe interface 100. The first PCIe device 1000 and thesecond PCIe device 2000 may establish a link, and the first PCIe device1000 and the second PCIe device 2000 may communicate through theestablished link. For example, the first PCIe device 1000 or the secondPCIe device 2000 may transmit and receive a packet according to the PCIeprotocol through the link.

FIG. 3 is a diagram illustrating a lane according to an embodiment ofthe present disclosure.

Referring to FIG. 3, a first transmitter TX1, a second transmitter TX2,a first receiver RX1, and a second receiver RX2 are illustrated. Thelane may include paths including differentially driven signal pairs,e.g., a transmission path pair configured for transmission and areception path pair configured for reception. A PCIe device may includetransmission logic for transmitting data to another PCIe device andreception logic for receiving data from another PCIe system. Forexample, the PCIe device may include two transmission paths coupled tothe first transmitter TX1 and two reception paths coupled to the firstreceiver RX1.

Here, the transmission path may mean any path for transmitting data,such as a transmission line, a copper line, an optical line, a wirelesscommunication channel, an infrared communication link, or any othercommunication paths. The reception path is implemented in the same wayas the transmission path, but may be a path used for reception.

The connection between two devices, e.g., between the first PCIe device1000 and the second PCIe device 2000, may be referred to as a link.

The link may support one or more lanes. Each of the lanes may representa set of differential signal pairs (one pair for transmission and theother pair for reception). The link may include a plurality of lanes inorder to adjust the bandwidth. For example, the link may include 1, 2,4, 8, 12, 16, 32 or 64 lanes.

FIG. 4 is a diagram illustrating a PCIe interface according to anembodiment of the present disclosure. Each of the layers included in thePCIe interface may include two sections. One of the sections may be asection for processing the outbound information (or the information tobe transmitted), and the other one may be a section for processing theinbound (or received) information. For example, when the first PCIeinterface 100 transmits data to the second PCIe interface 200 using thesection for processing the outbound information (or the information tobe transmitted), the second PCIe interface 200 may process thetransmitted data using the section for processing the inbound (orreceived) information.

Also, the PCIe interface may use packets in order to communicate datawith another PCIe interface.

Referring to FIG. 4, the first PCIe interface 100 and the second PCIeinterface 200 are illustrated. The PCIe layers included in each of thefirst PCIe interface 100 and the second PCIe interface 200 may includethree discrete logical layers. Specifically, the first PCIe interface100 may include a PCIe core 110, a transaction layer 120, a data linklayer 130, and a physical layer 140. The second PCIe interface 200 mayinclude a PCIe core 210, a transaction layer 220, a data link layer 230,and a physical layer 240. That is, the first PCIe interface 100 and thesecond PCIe interface 200 may be formed with the same structure, andthus a description will be made based on the first PCIe interface 100hereinbelow.

The PCIe core 110 may generally control the first PCIe interface 100.Specifically, the PCIe core 110 may include a software layer foroperating the first PCIe interface 100. Also, the PCIe core 110 maytransmit an address, a transaction type, data, and the like to thetransaction layer 120, or may receive an address, a transaction type,data, and the like from the transaction layer 120.

In the structure of the PCIe interface, an upper layer may be thetransaction layer 120. The transaction layer 120 may assembly ordisassembly transaction layer packets (TLPs). Also, the transactionlayer 120 may implement a split transaction, that is, a transaction bywhich, while a target system is collecting data required for a response,traffic other than that can be transmitted through a link. For example,the transaction layer 120 may implement a transaction in which a requestand a response are separated by time. In an embodiment, four transactionaddress spaces may include a configuration address space, a memoryaddress space, an input/output address space, and a message addressspace. A memory space transaction may include one or more of a readrequest and a write request for delivering data to/from a memory-mappedplace. In an embodiment, the memory space transaction may use twodifferent address formats, e.g., a short address format such as a 32-bitaddress or a long address format such as a 64-bit address. Aconfiguration space transaction may be used to access the configurationspace of the PCIe device. The transaction to the configuration space mayinclude a read request and a write request. A message space transaction(or message) may be defined to support in-band communication betweenPCIe devices. The transaction layer 120 may store link configurationinformation and the like received from the PCIe core 110. Also, thetransaction layer 120 may generate a TLP requested by the PCIe core 110,or may convert a received TLP into a payload or status information.

In the structure of the PCIe interface, a middle layer is the data linklayer 130, and the data link layer 130 may function as the intermediatestage between the transaction layer 120 and the physical layer 140. Themain function of the data link layer 130 may be link management and dataintegrity, including error detection and error correction. Specifically,the transmission side of the data link layer 130 may accept TLPsassembled by the transaction layer 120, assign a data protection code,or calculate a TLP sequence number. Also, the transmission side of thedata link layer 130 may transmit the data protection code and the TLPsequence number to the physical layer 140 for transmission over a link.The reception side of the data link layer 130 may check data integrityof TLPs received from the physical layer 140, and may transmit the TLPsto the transaction layer 120 for additional processing.

The physical layer 140 may include all circuitry for interfaceoperations. Here, all circuitry may include a driver, an input buffer, aseries-to-parallel conversion circuit, a parallel-to-series conversioncircuit, a phase-locked loop (PLL), and an impedance-matching circuit.

Also, the physical layer 140 may include a logical sub-block and anelectrical sub-block for physically transmitting a packet to an externalPCIe device. Here, the logical sub-block may act a role that isnecessary for a ‘digital’ function of the physical layer 140. Withregard to this, the logical sub-block may include a transmission sectionfor preparing the outgoing information to be transmitted by a physicalsub-block and a reception section for identifying and preparing thereceived information before delivering the received information to thedata link layer 130. The physical layer 140 may include a transmitter TXand a receiver RX. The transmitter TX may be supplied with symbols,which are serialized and transmitted to an external device by thetransmitter, from the logical sub-block. Also, the receiver RX may besupplied with serialized symbols from the external device, and mayconvert the received signal into a bitstream. The bitstream may bedeserialized and supplied to the logical sub-block. That is, thephysical layer 140 may convert the TLPs received from the data linklayer 130 into a serialized format, and may convert the packets receivedfrom the external device into a deserialized format. Also, the physicallayer 140 may include logical functions related to interfaceinitialization and maintenance.

The structures of the first PCIe interface 100 and the second PCIeinterface 200 are illustrated in FIG. 4, but an arbitrary form, such asa quick-path interconnect structure, a next-generation high-performancecomputing interconnect structure, or any other hierarchized structures,may be included.

FIG. 5 is a diagram illustrating the configuration of a packet 50according to an embodiment of the present disclosure.

Referring to FIG. 5, the respective components of the packet 50 may besequentially processed at the respective layers of a PCIe interface.

Specifically, the packet 50 may configure different protocols as theformats processed at the respective layers. For example, a transactionlayer packet (TLP) may be generated and processed at the transactionlayer 120 or 220, and the TLP may include a header field, a data field,and an ECRC field. Here, the header field may be a field including thetype of the TLP, information about whether data is included and whethera CRC is included, and the like. Also, the data field may be a fieldincluding the data to be transmitted or received, and the ECRC field maybe a field including an end-to-end cyclic redundancy check (ECRC) valueindicating information about an endpoint. Moreover, the data field andthe ECRC field may not be included in the TLP.

Also, a data link layer packet (DLLP) may be generated and processed atthe data link layer 130 or 230. The DLLP may further include a sequencenumber field and an LCRC field in addition to the TLP. Here, thesequence number field may be a field including information about thesequence number of the TLP, and the LCRC field may be a field includinginformation about a link cyclic redundancy check (LCRC).

Also, a physical layer packet (PLP) may be generated and processed atthe physical layer 140 or 240. The PLP may further include a framingfield in addition to the DLLP. Here, the framing field may be a fieldincluding information about a serialized format.

FIG. 6 is a diagram illustrating a DLLP according to an embodiment ofthe present disclosure.

Referring to FIG. 6, the fields that a data link layer packet (DLLP)must include according to a PCIe rule are illustrated. Specifically, aDLLP may include a type field 61, a support field 62, and a cyclicredundancy check (CRC) field 63.

The type field 61 may be a field indicating the type of the DLLP. Here,the type of the DLLP may include various functions such as anacknowledge (Ack) function for delivering an acknowledgement responsefrom the reception side to the transmission side, a negative acknowledge(Nak) function for delivering a negative acknowledgement response, apower management function, and the like. Also, the various functions ofthe DLLP may be identified using the value encoded in the type field 61.

TABLE 1 Encodings(b) DLLP Type 0000 0000 Ack 0000 0001 MRInit 0000 0010Data_Link_Feature 0001 0000 Nak 0010 0000 PM_Enter_L1 0010 0001PM_Enter_L1 0010 0011 PM_Active_State_Request_L1 0010 0100PM_Request_Ack 0011 0000 Vendor-specific 0011 0001 NOP 0100 0_(V2V1V0)InitFC1-P 0101 0_(V2V1V0) InitFC1-NP 0110 0_(V2V1V0) InitFC1-cpl

Table 1 includes the values of the DLLP types that are encoded accordingto the PCIe rule. However, Table 1 illustrates only a part of the DLLPtypes, and the encoded values can be changed according to a future PCIerule. The support field 62 may include different data depending on theDLLP type. That is, the support field 62 may include data correspondingto the type field 61. For example, when the type field 61 is the typecorresponding to Ack or Nak, the support field 62 may includeinformation about the sequence number corresponding to the Ack or Nak.

The CRC field 63 may be a field that must be included in the DLLP. Also,the CRC field 63 may be a field for ensuring (or checking) the dataintegrity of the DLLP. Specifically, the receiver of the DLLP maycompare the CRC value of the DLLP calculated using a preset method withthe CRC field 63, and may ensure the data integrity depending on whetherthe CRC field 63 includes the same value as the calculated CRC value.That is, the CRC field 63 may be calculated based on the preset method,and the data integrity of the DLLP may be ensured using the result ofcalculation of the CRC field 63.

FIG. 7 is a diagram illustrating the structure of a No Operation (NOP)DLLP according to an embodiment of the present disclosure.

Referring to FIG. 7, the format of a NOP DLLP is illustrated.Specifically, a NOP DLLP may include a type field 71 indicating the typeof the DLLP, a support field 72 according to the NOP DLLP, and a CRCfield. As described with reference to FIG. 6, the type field 71 mayinclude that is the value encoded to indicate the NOP DLLP, among thevarious functions of the DLLP. The support field 72 may include anarbitrary value. A conventional NOP DLLP is discarded without anyspecial action after data integrity is checked, and the arbitrary valueincluded in the support field 72 is used only for the purpose ofcalculating a CRC. Furthermore, when a compatibility issue occurs in anyof PCIe devices communicating with each other, it may be necessary tospecify the exact time at which the issue has occurred for accuratedebugging.

According to an embodiment of the present disclosure, a PCIe device mayannounce whether an event occurs with information about the event toanother PCIe device on the reception side using a NOP DLLP. Also, thePCIe device dumps the packet and data at the time of transmitting andreceiving the NOP DLLP, thereby handling the occurring event. Here,‘dump’ may mean storing or outputting the content of a specific devicein or to another device in order to correct a program error or to checkdata.

FIG. 8 is a diagram illustrating event information according to anembodiment of the present disclosure.

Referring to FIG. 8, a NOP DLLP including event information thatrepresents an event is illustrated. According to an embodiment of thepresent disclosure, a PCIe device may notify an additional PCIe deviceof an event occurring during communication with the additional PCIedevice. Specifically, some of the bits of the support field (e.g., 72 ofFIG. 7) of a NOP DLLP may be assigned for the information about theevent. Also, when an event occurs during communication with theadditional PCIe device, the PCIe device may transmit a NOP DLLPincluding information about the event to the additional PCIe device. Forexample, the support field of the NOP DLLP may be configured with 24bits, and each of the bits of the support field of the NOP DLLP maycorrespond to each possible event. Also, the PCIe device sets any bit ofthe support field of the NOP DLLP, thereby notifying the additional PCIedevice or a protocol analyzer of the occurrence of a specific event. Theadditional PCIe device and the protocol analyzer may detect that thetime of receiving the NOP DLLP transmitted from the PCIe device is thetime at which the specific event has occurred, and the additional PCIedevice and the protocol analyzer may use the corresponding time as thetrigger point at which to dump packets and data. That is, upon receivingthe NOP DLLP from the PCIe device, the additional PCIe device and theprotocol analyzer may dump the packets and data that are communicated.

According to an embodiment of the present disclosure, the support fieldof a NOP DLLP may represent event information. For example, the firstbit 81 of the support field of the NOP DLLP may be a bit indicating thatan unexpected decrease in the data transmission speed is caused due tothe timeout of a link training & status state machine (LTSSM). When adecrease in the speed is caused due to the timeout of the LTSSM, thePCIe device may transmit a NOP DLLP, in which the first bit 81 is set,to the additional PCIe device and the protocol analyzer. Accordingly,the additional PCIe device and the protocol analyzer may detect that adecrease in the speed is caused due to the timeout of the LTSSM includedin the PCIe device by referring to the event information in the receivedNOP DLLP.

According to an embodiment of the present disclosure, the support fieldof the NOP DLLP may include information about a plurality of events.Specifically, the event information may include information such as thereduction of lanes due to the timeout of an LTSSM, the occurrence oflink-down due to the timeout of the LTSSM, the occurrence of an internalparity error, the completion of post-processing of a parity error, theperformance of a temperature rise prevention operation caused due to atemperature rise, the termination of the temperature rise preventionoperation, and the like. Also, the PCIe device transmits a NOP DLLP inwhich the second bit 82, corresponding to ‘the occurrence of an internalparity error’, and the third bit 83, corresponding to ‘the performanceof a temperature rise prevention operation caused due to a temperaturerise’, are set, thereby transmitting event information corresponding tothe plurality of events to the additional PCIe device and the protocolanalyzer.

FIG. 9 is a diagram illustrating event information according to anembodiment of the present disclosure.

Referring to FIG. 9, the support field of a NOP DLLP, in which aplurality of bits are set, is illustrated. A method of mapping each ofthe bits included in the support field of a NOP DLLP to a single eventis described in FIG. 8, but according to an embodiment of the presentdisclosure, a PCIe device may represent information about a single eventusing a NOP DLLP including event information. Specifically, the PCIedevice may represent information corresponding to 2²⁴ bits using amethod of setting a plurality of bits in the support field of a NOPDLLP. For example, the PCIe device may indicate that a specific eventoccurs by setting the support field of a NOP DLLP to“000000001000100000000111”.

FIG. 10 is a diagram illustrating a link state of a PCIe deviceaccording to an embodiment of the present disclosure.

Referring to FIG. 10, the link states of a PCIe device may includestates such as a detect state, a polling state, a configuration state, ahot reset state, a disabled state, an L0 state, and the like.

The detect state is an initial state after power-on or reset, and may beentered from the states to be described below. For example, the detectstate may be the state entered from the configuration state, the hotreset state, the disabled state, the L2 state, the loopback state, orthe recovery state. In the detect state, all of logic, ports, andregisters may be reset, and the detect state may be the state in whichthe operation of detecting a link coupled to a PCIe interface isperformed. That is, in the detect state, the operation of searching fora physically coupled lane is performed.

The polling state may indicate the state in which a lane through whichdata communication is possible, among the detected lanes, is identified.The polling state may be the state in which the operations ofsynchronizing the clocks of the opposite ends of the PCIe interface,checking whether the polarity of the lane is D+or D−, and checking thedata transmission speed that the lane is able to use are performed. Thatis, the polling state may be the state in which polarity inversion ischecked. Also, the link in the polling state may enter the detect stateand the configuration state.

The configuration state may be the state in which the connection stateof the lane is checked. Specifically, the configuration state may be thestate in which the lane width with which data communication is possibleis determined. Also, the configuration state may be the state in whichthe operation of checking lane reverse is performed. The configurationstate may be entered from the poling state, or may be entered when lanesare reduced (lane reduce) or the lane width is increased (lane width up)after entry into the L0 state.

The recovery state may be the state used to reconfigure the linkbandwidth. In the recovery state, the set link bandwidth of the link maybe changed, and bit lock, symbol lock, and lane-to-lane de-skew may bereconfigured. The recovery state may be entered when an error occurs inthe L0 state, and when the error is recovered in the recovery state,transition into the L0 state may be performed. Also, according to anembodiment of the present disclosure, a link equalization operation maybe performed in the recovery state.

The L0 state may be a normal operation state in which data and packetscan be transmitted and received through a link. Specifically, the L0state may be the state in which a physical bus interface operates toenable data and control packet to be transmitted and received.

The L0s state is a power saving state that allows the physical businterface to quickly enter a power conservation state and to recovertherefrom without going through the recovery state.

The L1 state may be a power saving state. Power may be actively saved inthe L2 state. Most of the transmitter and receiver may be shut off. Mainpower and clocks are not ensured, but auxiliary power is available.

The loopback state may be the state for using test and fault isolation.Loopback is operated on a lane basis, and a loopback reception lane hasto be selected and configured.

The disabled state may be a state in which the configured link isdisabled until directed. The hot reset state may be triggered only by adownstream port. The downstream port may use training sequences (e.g.,TS1 or TS2) in order to propagate hot reset. Here, the trainingsequences (TS) may be ordered sets used for initializing bit alignment,symbol alignment, and exchange of physical layer parameters.

FIG. 11 is a diagram illustrating a protocol analyzer 500, which iscoupled to PCIe devices, according to an embodiment of the presentdisclosure.

Referring to FIG. 11, a first PCIe device 1000, a second PCIe device2000, and the protocol analyzer 500 are illustrated.

The first PCIe device 1000 and the second PCIe device 2000 may transmitand receive data or packets through a link. Here, the link may include aplurality of lanes. The first PCIe device 1000 may include an upstreamport 145, and the second PCIe device 2000 may include a downstream port245. The first PCIe device 1000 and the second PCIe device 2000 maysupport upstream routing and downstream routing using the upstream port145 and the downstream port 245, respectively.

The protocol analyzer 500 may be coupled to the link to monitorcommunication between the first PCIe device 1000 and the second PCIedevice 2000. Also, the protocol analyzer 500 may dump the upstreamrouting or downstream routing of the first PCIe device 1000 and thesecond

PCIe device 2000 at a specific time. Here, ‘dump’ may indicate storingor outputting not only data that is being transmitted but alsoinformation about a communication environment in or to the protocolanalyzer 500 in order to correct a program error or to check data.Specifically, when it detects transmission of a NOP DLLP from the firstPCIe device 1000 or the second PCIe device 2000, the protocol analyzer500 may dump the data or packets transmitted during a fixed time periodincluding the time at which the detected NOP DLLP is transmitted. Theprotocol analyzer 500 may dump data or packets transmitted not only fromthe PCIe device in which the event occurs but also from a PCIe device inwhich no event occurs.

In an embodiment, when an event occurs in the first PCIe device 1000,the first PCIe device 1000 may transmit a NOP DLLP including informationabout the event to the second PCIe device 2000. Also, the first PCIedevice 1000 may dump the state of the first PCIe device 1000 during afixed time period including the specific time at which the event hasoccurred. Then, when the protocol analyzer 500 or the second PCIe device2000 detects the NOP DLLP transmitted from the first PCIe device 1000,it may dump data or packets that are transmitted during a fixed timeperiod including the time at which the detected NOP DLLP is transmitted.The first PCIe device 1000, the second PCIe device 2000, and theprotocol analyzer 500 may store the transmitted data and packets byregarding the specific time at which the event has occurred as a triggerpoint. Then, the first PCIe device 1000, the second PCIe device 2000,and the protocol analyzer 500 may perform accurate debugging related tothe event by synchronizing the specific time at which the event hasoccurred.

FIG. 12 is a diagram illustrating a first PCIe interface 100 accordingto an embodiment of the present disclosure.

Referring to FIG. 12, the first PCIe interface 100 may include atransceiver 150, a NOP DLLP generator 160, and a register storage 170.

The transceiver 150 may be the component for transmitting and receivingpackets to and from an additional PCIe device. The transceiver 150 maybe coupled to the additional PCIe device through a link including aplurality of lanes. Also, the transceiver 150 may transmit and receivepackets to and from the additional PCIe device using the link. Accordingto an embodiment of the present disclosure, the transceiver 150 maytransmit a NOP DLLP to the additional PCIe device through the link.According to an embodiment, the transceiver 150 may repeatedly transmitthe NOP DLLP during a preset time period. Specifically, in order toprevent the case where the additional PCIe device configured to receivethe NOP DLLP cannot receive the transmitted NOP DLLP, the transceiver150 may repeatedly transmit the NOP DLLP during the preset time period.

The NOP DLLP generator 160 may be the component configured to generate aNOP DLLP. Specifically, when an event occurs in the PCIe device, the NOPDLLP generator 160 may generate a NOP DLLP including event informationcorresponding to the occurring event. Here, the event information may beinformation indicating the occurrence of the event. In some embodiments,the event may include at least one of reduction of lanes due to thetimeout of an LTSSM, the occurrence of link-down due to the timeout ofthe LTSSM, the occurrence of an internal parity error, the completion ofpost-processing of a parity error, the performance of a temperature riseprevention operation caused due to a temperature rise, and thetermination of the temperature rise prevention operation caused due tothe temperature rise. In an embodiment, the NOP DLLP generator 160 mayrepresent the event information by setting at least one bit of thesupport field of the NOP DLLP. Also, the NOP DLLP generator 160 mayalternatively generate a NOP DLLP in which the bits included in thesupport field of the NOP DLLP respectively correspond to a plurality ofevents. The NOP DLLP generator 160 may alternatively generate a NOP DLLPcorresponding to a single event using all of the bits included in thesupport field of the NOP DLLP.

In response to the occurrence of the event, the register storage 170 maystore data transmitted and received during a preset time periodincluding the occurrence time of the event and information about thecommunication environment. The register storage 170 may store not onlydata transmitted from the PCIe device to the additional PCIe device butalso information about the received data. Also, the information storedin the register storage 170 is compared with information stored in theadditional PCIe device or a protocol analyzer, whereby an accuratedebugging operation for the occurring event may be performed.

The present disclosure provides a PCIe interface device capable ofdetecting the trigger points of occurring events using a NOP DLLP and asystem including the PCIe interface device.

Various embodiments of the present disclosure have been described in thedrawings and specification. Although specific terminologies are usedhere, those are only to describe the embodiments of the presentdisclosure. Therefore, the present disclosure is not restricted to theabove-described embodiments and many variations are possible within thespirit and scope of the present disclosure. It should be apparent tothose skilled in the art that various modifications can be made on thebasis of the technological scope of the present disclosure in additionto the embodiments disclosed herein and the following claims. Theembodiments may be combined to form additional embodiments.

What is claimed is:
 1. A peripheral component interconnect express(PCIe) interface device, comprising: a No Operation (NOP) data linklayer packet (DLLP) generator configured to generate a NOP DLLPincluding event information representing an event in response tooccurrence of the event; and a transmitter configured to transmit theNOP DLLP to an external device through a link including a plurality oflanes.
 2. The PCIe interface device according to claim 1, wherein theNOP DLLP includes a support field including a plurality of bits and theNOP DLLP generator represents the event information by setting at leastone bit of the support field of the NOP DLLP.
 3. The PCIe interfacedevice according to claim 2, wherein the NOP DLLP generator generatesthe NOP DLLP in which the bits in the support field of the NOP DLLPrespectively correspond to a plurality of events.
 4. The PCIe interfacedevice according to claim 2, wherein the NOP DLLP generator generatesthe NOP DLLP corresponding to a single event using all of the bits inthe support field of the NOP DLLP.
 5. The PCIe interface deviceaccording to claim 1, wherein the transmitter repeatedly transmits theNOP DLLP during a preset time period.
 6. The PCIe interface deviceaccording to claim 1, further comprising: a register storage configuredto store data, transmitted and received during a preset time periodincluding an occurrence time of the event, and information about acommunication environment in response to the occurrence of the event. 7.The PCIe interface device according to claim 1, wherein the eventincludes at least one of reduction of lanes due to a timeout of a linktraining and status state machine (LTSSM), occurrence of link-down dueto the timeout of the LTSSM, occurrence of an internal parity error,completion of post-processing of a parity error, performance of atemperature rise prevention operation caused due to a temperature rise,and termination of the temperature rise prevention operation caused dueto the temperature rise.
 8. A peripheral component interconnect express(PCIe) system, comprising: a first PCIe device configured to generate aNo Operation (NOP) data link layer packet (DLLP) including eventinformation representing an event in response to occurrence of the eventand to transmit the NOP DLLP through a link including a plurality oflanes; and a second PCIe device configured to, when the NOP DLLP isreceived from the first PCIe device, perform a dump operation forstoring information about data and packets transmitted and receivedduring a set time period including a time at which the NOP DLLP isreceived.
 9. The PCIe system according to claim 8, wherein the NOP DLLPincludes a support field including a plurality of bits and the firstPCIe device represents the event information by setting at least one bitof the support field of the NOP DLLP.
 10. The PCIe system according toclaim 9, wherein the first PCIe device generates the NOP DLLP in whichthe bits in the support field of the NOP DLLP respectively correspond toa plurality of events.
 11. The PCIe system according to claim 9, whereinthe first PCIe device generates the NOP DLLP corresponding to a singleevent using all of the bits in the support field of the NOP DLLP. 12.The PCIe system according to claim 8, wherein the first PCIe devicerepeatedly transmits the NOP DLLP during a preset time period.
 13. ThePCIe system according to claim 8, wherein the first PCIe device storesdata, transmitted and received during a preset time period including anoccurrence time of the event, and information about a communicationenvironment in response to the occurrence of the event.
 14. The PCIesystem according to claim 8, wherein the event includes at least one ofreduction of lanes due to a timeout of a link training and status statemachine (LTSSM), occurrence of link-down due to the timeout of theLTSSM, occurrence of an internal parity error, completion ofpost-processing of a parity error, performance of a temperature riseprevention operation caused due to a temperature rise, and terminationof the temperature rise prevention operation caused due to thetemperature rise.
 15. A peripheral component interconnect express (PCIe)system, comprising: a first PCIe device configured to generate a NoOperation (NOP) data link layer packet (DLLP) including eventinformation representing an event in response to occurrence of the eventand to transmit the NOP DLLP through a link including a plurality oflanes; a second PCIe device coupled to the first PCIe device through thelink and configured to transmit and receive a packet including the NOPDLLP to and from the first PCIe device; and a protocol analyzer coupledto the link and configured to monitor the packet transmitted andreceived between the first PCIe device and the second PCIe devicethrough the link and to perform a dump operation for storing informationabout a communication environment based on the event information whendetecting the NOP DLLP.
 16. The PCIe system according to claim 15,wherein the NOP DLLP includes a support field including a plurality ofbits and the first PCIe device represents the event information bysetting at least one bit of the support field of the NOP DLLP.
 17. ThePCIe system according to claim 16, wherein the first PCIe devicegenerates the NOP DLLP in which the bits in the support field of the NOPDLLP respectively correspond to a plurality of events.
 18. The PCIesystem according to claim 16, wherein the first PCIe device generatesthe NOP DLLP corresponding to a single event using all of the bits inthe support field of the NOP DLLP.
 19. The PCIe system according toclaim 15, wherein the first PCIe device stores data, transmitted andreceived during a preset time period including an occurrence time of theevent, and information about a communication environment in response tothe occurrence of the event.
 20. The PCIe system according to claim 15,wherein the event includes at least one of reduction of lanes due to atimeout of a link training and status state machine (LTSSM), occurrenceof link-down due to the timeout of the LTSSM, occurrence of an internalparity error, completion of post-processing of a parity error,performance of a temperature rise prevention operation caused due to atemperature rise, and termination of the temperature rise preventionoperation caused due to the temperature rise.